/*--------------------------------------------------------------------------
CC1110.H
Registers definition for ChipCon CC1110

Copyright (c) 2006 Keil - An ARM Company
All rights reserved.
-------------------------------------------------------------------------- */

/* Byte Addresses */
sfr   P0    	 = 0x80;
sfr   SP    	 = 0x81;
sfr   DPL0   	 = 0x82;
sfr   DPH0   	 = 0x83;
sfr   DPL1   	 = 0x84;
sfr   DPH1   	 = 0x85;
sfr   U0CSR   	 = 0x86;
sfr   PCON   	 = 0x87;
sfr   TCON   	 = 0x88;
sfr   P0IFG   	 = 0x89;
sfr   P1IFG   	 = 0x8A;
sfr   P2IFG   	 = 0x8B;
sfr   PICTL   	 = 0x8C;
sfr   P1IEN   	 = 0x8D;
sfr   P0INP   	 = 0x8F;
sfr   P1    	 = 0x90;
sfr   RFIM   	 = 0x91;
sfr   DPS   	 = 0x92;
sfr   MPAGE   	 = 0x93;
sfr   S0CON   	 = 0x98;
sfr   IEN2   	 = 0x9A;
sfr   S1CON   	 = 0x9B;
sfr   T2TC   	 = 0x9C;
sfr   T2PR   	 = 0x9D;
sfr   T2CTL   	 = 0x9E;
sfr   P2    	 = 0xA0;
sfr   WORIRQ   	 = 0xA1;
sfr   WORCTL   	 = 0xA2;
sfr   WOREVT0   	 = 0xA3;
sfr   WOREVT1   	 = 0xA4;
sfr   WORTIME0   	 = 0xA5;
sfr   WORTIME1   	 = 0xA6;
sfr   IEN0   	 = 0xA8;
sfr   IP0   	 = 0xA9;
sfr   FWT   	 = 0xAB;
sfr   FADDRL   	 = 0xAC;
sfr   FADDRH   	 = 0xAD;
sfr   FCTL   	 = 0xAE;
sfr   FWDATA   	 = 0xAF;
sfr   ENCDI   	 = 0xB1;
sfr   ENCDO   	 = 0xB2;
sfr   ENCCS   	 = 0xB3;
sfr   ADCCON1   	 = 0xB4;
sfr   ADCCON2   	 = 0xB5;
sfr   ADCCON3   	 = 0xB6;
sfr   IEN1   	 = 0xB8;
sfr   IP1   	 = 0xB9;
sfr   ADCL   	 = 0xBA;
sfr   ADCH   	 = 0xBB;
sfr   RNDL   	 = 0xBC;
sfr   RNDH   	 = 0xBD;
sfr   SLEEP   	 = 0xBE;
sfr   IRCON   	 = 0xC0;
sfr   U0DBUF   	 = 0xC1;
sfr   U0BAUD   	 = 0xC2;
sfr   U0UCR   	 = 0xC4;
sfr   U0GCR   	 = 0xC5;
sfr   CLKCON   	 = 0xC6;
sfr   MEMCTR   	 = 0xC7;
sfr   WDCTL   	 = 0xC9;
sfr   T3CNT   	 = 0xCA;
sfr   T3CTL   	 = 0xCB;
sfr   T3CCTL0   	 = 0xCC;
sfr   T3CC0   	 = 0xCD;
sfr   T3CCTL1   	 = 0xCE;
sfr   T3CC1   	 = 0xCF;
sfr   PSW   	 = 0xD0;
sfr   DMAIRQ   	 = 0xD1;
sfr   DMA1CFGL   	 = 0xD2;
sfr   DMA1CFGH   	 = 0xD3;
sfr   DMA0CFGL   	 = 0xD4;
sfr   DMA0CFGH   	 = 0xD5;
sfr   DMAARM   	 = 0xD6;
sfr   DMAREQ   	 = 0xD7;
sfr   TIMIF   	 = 0xD8;
sfr   RFD   	 = 0xD9;
sfr   T1CC0L   	 = 0xDA;
sfr   T1CC0H   	 = 0xDB;
sfr   T1CC1L   	 = 0xDC;
sfr   T1CC1H   	 = 0xDD;
sfr   T1CC2L   	 = 0xDE;
sfr   T1CC2H   	 = 0xDF;
sfr   ACC   	 = 0xE0;
sfr   RFST   	 = 0xE1;
sfr   T1CNTL   	 = 0xE2;
sfr   T1CNTH   	 = 0xE3;
sfr   T1CTL   	 = 0xE4;
sfr   T1CCTL0   	 = 0xE5;
sfr   T1CCTL1   	 = 0xE6;
sfr   T1CCTL2   	 = 0xE7;
sfr   IRCON2   	 = 0xE8;
sfr   RFIF   	 = 0xE9;
sfr   T4CNT   	 = 0xEA;
sfr   T4CTL   	 = 0xEB;
sfr   T4CCTL0   	 = 0xEC;
sfr   T4CC0   	 = 0xED;
sfr   T4CCTL1   	 = 0xEE;
sfr   T4CC1   	 = 0xEF;
sfr   B      	 = 0xF0;
sfr   PERCFG   	 = 0xF1;
sfr   ADCCFG   	 = 0xF2;
sfr   P0SEL   	 = 0xF3;
sfr   P1SEL   	 = 0xF4;
sfr   P2SEL   	 = 0xF5;
sfr   P1INP   	 = 0xF6;
sfr   P2INP   	 = 0xF7;
sfr   U1CSR   	 = 0xF8;
sfr   U1DBUF   	 = 0xF9;
sfr   U1BAUD   	 = 0xFA;
sfr   U1UCR   	 = 0xFB;
sfr   U1GCR   	 = 0xFC;
sfr   P0DIR   	 = 0xFD;
sfr   P1DIR   	 = 0xFE;
sfr   P2DIR   	 = 0xFF;


/* Bit Addresses */

/* TCON */
sbit   IT0   	 = TCON^0;
sbit   IE0   	 = TCON^1;
sbit   IT1   	 = TCON^2;
sbit   IE1   	 = TCON^3;
sbit   TR0   	 = TCON^4;
sbit   TF0   	 = TCON^5;
sbit   TR1   	 = TCON^6;
sbit   TF1   	 = TCON^7;

/* S0CON */
sbit   RI   	 = S0CON^0;
sbit   TI   	 = S0CON^1;
sbit   RB8   	 = S0CON^2;
sbit   TB8   	 = S0CON^3;
sbit   REN   	 = S0CON^4;
sbit   SM3   	 = S0CON^5;
sbit   SM1   	 = S0CON^6;
sbit   SM0   	 = S0CON^7;

/* IEN0 */
sbit   EX0   	 = IEN0^0;
sbit   ET0   	 = IEN0^1;
sbit   EX1   	 = IEN0^2;
sbit   ET1   	 = IEN0^3;
sbit   ES   	 = IEN0^4;
sbit   EA   	 = IEN0^7;

/* IEN1 */
sbit   PX0   	 = IEN1^0;
sbit   PT0   	 = IEN1^1;
sbit   PX1   	 = IEN1^2;
sbit   PT1   	 = IEN1^3;
sbit   PS   	 = IEN1^4;

/* PSW */
sbit   P   	 = PSW^0;
sbit   OV   	 = PSW^2;
sbit   RS0   	 = PSW^3;
sbit   RS1   	 = PSW^4;
sbit   F0   	 = PSW^5;
sbit   AC   	 = PSW^6;
sbit   CY   	 = PSW^7;

