******************************************************************************************
                               PSDsoft Express Version 8.30
                                   Output of PSD Fitter
******************************************************************************************
  PROJECT    : project                          DATE : 10/08/2004
  DEVICE     : uPSD3334D                        TIME : 12:02:12
  FIT OPTION : Keep Current
  DESCRIPTION: Starting Template for New DK3300 E-LCD Projects

Main Flash 
               is located in Code Space: FS0 = 0000h, FS1..FS7 = Paged at 8000h

Boot 
               Flash is located in Data Space: BS0..BS3 = 8000h to FFFFh

SRAM 
               and CSIOP is located in Data Space: RS0 = 0000h CSIOP = 7F00h

E-LCD 
               is located in Data Space: 7E00h

 
******************************************************************************************
     ==== Pin Layout for U (80-Pin TQFP) Package Type ====

                                               -----------------------------
                                              |                             |
                                              |1 ] pd2             adio4 [41| Address Bus a4/Data Port d4, ad4
                                              |2 ] p3_3             p3_5 [42|  
                                              |3 ] pd1             adio5 [43| Address Bus a5/Data Port d5, ad5
                                          ale |4 ] pd0              p3_6 [44|  
                                              |5 ] pc7             adio6 [45| Address Bus a6/Data Port d6, ad6
                                     tdo, TDO |6 ] pc6/TDO          p3_7 [46|  
                                     tdi, TDI |7 ] pc5/TDI         adio7 [47| Address Bus a7/Data Port d7, ad7
                               JTAG_debug_pin |8 ] debug           Xtal1 [48| Xtal1
                                              |9 ] pc4/TERR        Xtal2 [49| Xtal2
                                              |10] 3.3V VCC     5.0V VCC [50|  
                                              |11] N/C             adio8 [51| Address Bus a8, a8
                                              |12] 5.0V VCC         p1_0 [52|  
                                              |13] GND             adio9 [53| Address Bus a9, a9
                                              |14] pc3/TSTAT        p1_1 [54|  
                                              |15] pc2            adio10 [55| Address Bus a10, a10
                                     tck, TCK |16] pc1/TCK          p1_2 [56|  
                                              |17] N/C            adio11 [57| Address Bus a11, a11
                                              |18] p4_7             p1_3 [58|  
                                              |19] p4_6             p1_4 [59|  
                                     tms, TMS |20] pc0/TMS          p1_5 [60|  
                     pa7 ,Peripheral I/O Mode |21] pa7              p1_6 [61|  
                     pa6 ,Peripheral I/O Mode |22] pa6             cntl0 [62| _wr
                                              |23] p4_5            cntl2 [63| _psen
                     pa5 ,Peripheral I/O Mode |24] pa5              p1_7 [64|  
                                              |25] p4_4            cntl1 [65| _rd
                     pa4 ,Peripheral I/O Mode |26] pa4               pb7 [66|  
                                              |27] p4_3              pb6 [67|  
                     pa3 ,Peripheral I/O Mode |28] pa3          Reset_In [68| _Reset_In
                                              |29] GND               GND [69|  
                                              |30] p4_2             Vref [70| VREF
                                              |31] p4_1              pb5 [71|  
                     pa2 ,Peripheral I/O Mode |32] pa2              AVcc [72|  
                                              |33] p4_0              pb4 [73| LCD_E2
                     pa1 ,Peripheral I/O Mode |34] pa1               pb3 [74| LCD_E1
                     pa0 ,Peripheral I/O Mode |35] pa0              p3_0 [75|  
             ad0, Address Bus a0/Data Port d0 |36] adio0             pb2 [76| LCD_RW
             ad1, Address Bus a1/Data Port d1 |37] adio1            p3_1 [77|  
             ad2, Address Bus a2/Data Port d2 |38] adio2             pb1 [78| LCD_A0
             ad3, Address Bus a3/Data Port d3 |39] adio3            p3_2 [79|  
                                              |40] p3_4              pb0 [80|  
                                              |                             |
                                               -----------------------------
     ==== Global Configuration ====

Data Bus                                                         : 8-Bit
Address/Data Mode                                                : Multiplexed
ALE/AS Signal                                                    : Active High
Control Signals                                                  : /WR, /RD, /PSEN
Main PSD flash memory will reside in this space at power-up      : Program space
Secondary PSD flash memory will reside in this space at power-up : Data space
Enable Chip-Select Input(/CSI)                                   : OFF
Standby Voltage Input (PC2)                                      : OFF
Standby-on Indicator (PC4)                                       : OFF
RDY/Busy function (PC3)                                          : OFF
Load Micro-Cell on                                               : edge
Security Protection                                              : OFF 

     ==== DataBus_IMC access information ====

                  CSIOP
Location     Address Offset     Register Name           Signals
--------------------------------------------------------

     ===== Resource Usage Summary =====

Total Product Terms Used:  26

Device Resources                    used / total
------------------------------------------------
Port A: (pins 35 34 32 28 26 24 22 21)
I/O Pins :                           8   /  8 
   GP I/O or Address Out        :    0 
   Peripheral I/O               :    8 
   Logic Inputs                 :    0 
   Address Latch Inputs         :    0 
   PT Dependent Latch Inputs    :    0 
   PT Dependent Register Inputs :    0 
   Combinatorial Outputs        :    0 
   Registered Outputs           :    0 
Other Information
   Microcells                   :    0   /  8 
     Micro-Cells AB :
      Buried Microcells         :    0 
      Output Microcells         :    0 
   Product Terms                :    0   /  24
   Control Product Terms        :    0   /  34

Port B: (pins 80 78 76 74 73 71 67 66)
I/O Pins :                           4   /  8 
   GP I/O or Address Out        :    0 
   Logic Inputs                 :    0 
   Address Latch Inputs         :    0 
   PT Dependent Latch Inputs    :    0 
   PT Dependent Register Inputs :    0 
   Combinatorial Outputs        :    4 
   Registered Outputs           :    0 
Other Information
   Microcells                   :    4   /  8 
     Micro-Cells AB :
      Buried Microcells         :    0 
      Output Microcells         :    0 
     Micro-Cells BC :
      Buried Microcells         :    0 
      Output Microcells         :    4 
   Product Terms                :    6   /  28
   Control Product Terms        :    4   /  34

Port C: (pins 20 16 15 14 9 7 6 5)
I/O Pins :                           4   /  8 
   GP I/O or Address Out        :    0 
   Logic Inputs                 :    0 
   Address Latch Inputs         :    0 
   PT Dependent Latch Inputs    :    0 
   PT Dependent Register Inputs :    0 
   JTAG signals                 :    4 
   Standby Voltage Input        :    0 
   Rdy/Bsy signal               :    0 
   Standby On Indicator         :    0 
   Combinatorial Outputs        :    0 
   Registered Outputs           :    0 
Other Information
   Microcells                   :    4   /  8 
     Micro-Cells BC :
      Buried Microcells         :    4 
      Output Microcells         :    0 
   Product Terms                :    6   /  32
   Control Product Terms        :    0   /  34

Port D: (pins 4 3 1)
I/O Pins :                           1   /  3 
   GP I/O or Address Out        :    0 
   Logic Inputs                 :    0 
   Chip-Select Input            :    0 
   Clock Input                  :    0 
   Control Signal Input         :    1 
   Fast Decoding Outputs        :    0 
Other Information
   Product Terms                :    0   /  3 
   Control Product Terms        :    0   /  3 


     ==== OMC Resource Assignment ====

  Resources           PT             User
  Used                Allocation     Name
 ---------------------------------------------------------
Micro-Cell AB :

Micro-Cell BC :
  Micro-Cells 1        -             LCD_A0 (mcellbc1)  => Combinatorial
  Micro-Cells 2        -             LCD_RW (mcellbc2)  => Combinatorial
  Micro-Cells 3        -             LCD_E1 (mcellbc3)  => Combinatorial
  Micro-Cells 4        -             LCD_E2 (mcellbc4)  => Combinatorial

External Chip Select :


     ========= Equations =========

DPLD          EQUATIONS :
=======================
     fs0 = !pdn & !a15;

     fs1 = !pdn & !pgr2 & !pgr1 & !pgr0 & a15;

     fs2 = !pdn & !pgr2 & !pgr1 & pgr0 & a15;

     fs3 = !pdn & !pgr2 & pgr1 & !pgr0 & a15;

     fs4 = !pdn & !pgr2 & pgr1 & pgr0 & a15;

     fs5 = !pdn & pgr2 & !pgr1 & !pgr0 & a15;

     fs6 = !pdn & pgr2 & !pgr1 & pgr0 & a15;

     fs7 = !pdn & pgr2 & pgr1 & !pgr0 & a15;

     csboot0 = !pdn & a15 & !a14 & !a13;

     csboot1 = !pdn & a15 & !a14 & a13;

     csboot2 = !pdn & a15 & a14 & !a13;

     csboot3 = !pdn & a15 & a14 & a13;

     csiop = !pdn & !a15 & a14 & a13 & a12 & a11 & a10 & a9 & a8;

     rs0 = !pdn & !a15 & !a14 & !a13;

     psel0 = !pdn & _psen & !a15 & a14 & a13 & a12 & a11 & a10 & a9 & !a8;

     jtagsel = !_reset;

PORTA         EQUATIONS :
=======================
PORTB         EQUATIONS :
=======================
     LCD_A0 = a1;
     LCD_A0.OE = 1;

     LCD_RW = a0;
     LCD_RW.OE = 1;

     LCD_E1 = (!_wr & !a15 & a14 & a13 & a12 & a11 & a10 & a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & !a2)
          # (!_rd & !a15 & a14 & a13 & a12 & a11 & a10 & a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & !a2);
     LCD_E1.OE = 1;

     LCD_E2 = (!_wr & !a15 & a14 & a13 & a12 & a11 & a10 & a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & a2)
          # (!_rd & !a15 & a14 & a13 & a12 & a11 & a10 & a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & a2);
     LCD_E2.OE = 1;

PORTC         EQUATIONS :
=======================
PORTD         EQUATIONS :
=======================
                                      ---  End  ---
