;****************************************************************************
; Filename      DaveTest.asm
; Project       DaveTest.dav
;----------------------------------------------------------------------------
; Description   This file contains the assembler formatted information
;                about the actual project values. It will be used by your
;                programming environment.
;
;                PLEASE DO NOT MODIFY THIS FILE !
;
;----------------------------------------------------------------------------
; Date          09.02.2005 00:47:37
;
;****************************************************************************


; RMAP=0 PAGE=1 - ADC Channel 0 Control Register
ADC_CHCTR0_LCC	SET	0
ADC_CHCTR0_RESRSEL	SET	0

; RMAP=0 PAGE=1 - ADC Channel 1 Control Register
ADC_CHCTR1_LCC	SET	0
ADC_CHCTR1_RESRSEL	SET	0

; RMAP=0 PAGE=1 - ADC Channel 2 Control Register
ADC_CHCTR2_LCC	SET	0
ADC_CHCTR2_RESRSEL	SET	0

; RMAP=0 PAGE=1 - ADC Channel 3 Control Register
ADC_CHCTR3_LCC	SET	0
ADC_CHCTR3_RESRSEL	SET	0

; RMAP=0 PAGE=1 - ADC Channel 4 Control Register
ADC_CHCTR4_LCC	SET	0
ADC_CHCTR4_RESRSEL	SET	0

; RMAP=0 PAGE=1 - ADC Channel 5 Control Register
ADC_CHCTR5_LCC	SET	0
ADC_CHCTR5_RESRSEL	SET	0

; RMAP=0 PAGE=1 - ADC Channel 6 Control Register
ADC_CHCTR6_LCC	SET	0
ADC_CHCTR6_RESRSEL	SET	0

; RMAP=0 PAGE=1 - ADC Channel 7 Control Register
ADC_CHCTR7_LCC	SET	0
ADC_CHCTR7_RESRSEL	SET	0

; RMAP=0 PAGE=5 - ADC Channel Interrupt Clear Register
ADC_CHINCR_CHINC0	SET	0
ADC_CHINCR_CHINC1	SET	0
ADC_CHINCR_CHINC2	SET	0
ADC_CHINCR_CHINC3	SET	0
ADC_CHINCR_CHINC4	SET	0
ADC_CHINCR_CHINC5	SET	0
ADC_CHINCR_CHINC6	SET	0
ADC_CHINCR_CHINC7	SET	0

; RMAP=0 PAGE=5 - ADC Channel Interrupt Flag Register
ADC_CHINFR_CHINF0	SET	0
ADC_CHINFR_CHINF1	SET	0
ADC_CHINFR_CHINF2	SET	0
ADC_CHINFR_CHINF3	SET	0
ADC_CHINFR_CHINF4	SET	0
ADC_CHINFR_CHINF5	SET	0
ADC_CHINFR_CHINF6	SET	0
ADC_CHINFR_CHINF7	SET	0

; RMAP=0 PAGE=5 - ADC Channel Interrupt Node Pointer Register
ADC_CHINPR_CHINP0	SET	0
ADC_CHINPR_CHINP1	SET	0
ADC_CHINPR_CHINP2	SET	0
ADC_CHINPR_CHINP3	SET	0
ADC_CHINPR_CHINP4	SET	0
ADC_CHINPR_CHINP5	SET	0
ADC_CHINPR_CHINP6	SET	0
ADC_CHINPR_CHINP7	SET	0

; RMAP=0 PAGE=5 - ADC Channel Interrupt Set Register
ADC_CHINSR_CHINS0	SET	0
ADC_CHINSR_CHINS1	SET	0
ADC_CHINSR_CHINS2	SET	0
ADC_CHINSR_CHINS3	SET	0
ADC_CHINSR_CHINS4	SET	0
ADC_CHINSR_CHINS5	SET	0
ADC_CHINSR_CHINS6	SET	0
ADC_CHINSR_CHINS7	SET	0

; RMAP=0 PAGE=6 - ADC Source 1 Conversion Request Control Register
ADC_CRCR1_CH4	SET	0
ADC_CRCR1_CH5	SET	0
ADC_CRCR1_CH6	SET	0
ADC_CRCR1_CH7	SET	0

; RMAP=0 PAGE=6 - ADC Source 1 Conversion Request Mode Register
ADC_CRMR1_CLRPND	SET	0
ADC_CRMR1_ENGT	SET	0
ADC_CRMR1_ENSI	SET	0
ADC_CRMR1_ENTR	SET	0
ADC_CRMR1_LDEV	SET	0
ADC_CRMR1_SCAN	SET	0

; RMAP=0 PAGE=6 - ADC Source 1 Conversion Request Pending Register
ADC_CRPR1_CHP4	SET	0
ADC_CRPR1_CHP5	SET	0
ADC_CRPR1_CHP6	SET	0
ADC_CRPR1_CHP7	SET	0

; RMAP=0 PAGE=0 - ADC External Trigger Control Register
ADC_ETRCR_ETRSEL0	SET	0
ADC_ETRCR_ETRSEL1	SET	0
ADC_ETRCR_SYNEN0	SET	0
ADC_ETRCR_SYNEN1	SET	0

; RMAP=0 PAGE=5 - ADC Event Interrupt Clear Register
ADC_EVINCR_EVINC0	SET	0
ADC_EVINCR_EVINC1	SET	0
ADC_EVINCR_EVINC4	SET	0
ADC_EVINCR_EVINC5	SET	0
ADC_EVINCR_EVINC6	SET	0
ADC_EVINCR_EVINC7	SET	0

; RMAP=0 PAGE=5 - ADC Event Interrupt Flag Register
ADC_EVINFR_EVINF0	SET	0
ADC_EVINFR_EVINF1	SET	0
ADC_EVINFR_EVINF4	SET	0
ADC_EVINFR_EVINF5	SET	0
ADC_EVINFR_EVINF6	SET	0
ADC_EVINFR_EVINF7	SET	0

; RMAP=0 PAGE=5 - ADC Event Interrupt Node Pointer Register
ADC_EVINPR_EVINP0	SET	0
ADC_EVINPR_EVINP1	SET	0
ADC_EVINPR_EVINP4	SET	0
ADC_EVINPR_EVINP5	SET	0
ADC_EVINPR_EVINP6	SET	0
ADC_EVINPR_EVINP7	SET	0

; RMAP=0 PAGE=5 - ADC Event Interrupt Set Flag Register
ADC_EVINSR_EVINS0	SET	0
ADC_EVINSR_EVINS1	SET	0
ADC_EVINSR_EVINS4	SET	0
ADC_EVINSR_EVINS5	SET	0
ADC_EVINSR_EVINS6	SET	0
ADC_EVINSR_EVINS7	SET	0

; RMAP=0 PAGE=0 - ADC Global Control Register
ADC_GLOBCTR_ANON	SET	0
ADC_GLOBCTR_CTC	SET	3
ADC_GLOBCTR_DW	SET	0

; RMAP=0 PAGE=0 - ADC Global Status Register
ADC_GLOBSTR_BUSY	SET	0
ADC_GLOBSTR_CHNR	SET	0
ADC_GLOBSTR_SAMPLE	SET	0

; RMAP=0 PAGE=0 - ADC Input Class 0 Register
ADC_INPCR0_STC	SET	0

; RMAP=0 PAGE=0 - ADC Limit Check Boundary Register
ADC_LCBR_BOUND0	SET	7
ADC_LCBR_BOUND1	SET	11

; RMAP=0  - ADC Page Register
ADC_PAGE_OP	SET	0
ADC_PAGE_PAGE	SET	0
ADC_PAGE_STNR	SET	0

; RMAP=0 PAGE=0 - ADC Priority and Arbitration Register
ADC_PRAR_ARBM	SET	0
ADC_PRAR_ASEN0	SET	0
ADC_PRAR_ASEN1	SET	0
ADC_PRAR_CSM0	SET	0
ADC_PRAR_CSM1	SET	0
ADC_PRAR_PRIO0	SET	0
ADC_PRAR_PRIO1	SET	0

; RMAP=0 PAGE=6 - ADC Source 0 Queue 0 Register
ADC_Q0R0_ENSI	SET	0
ADC_Q0R0_EXTR	SET	0
ADC_Q0R0_REQCHNR	SET	0
ADC_Q0R0_RF	SET	0
ADC_Q0R0_V	SET	0

; RMAP=0 PAGE=6 - ADC Source 0 Queue Backup Register
ADC_QBUR0_ENSI	SET	0
ADC_QBUR0_EXTR	SET	0
ADC_QBUR0_REQCHNR	SET	0
ADC_QBUR0_RF	SET	0
ADC_QBUR0_V	SET	0

; RMAP=0 PAGE=6 - ADC Source 0 Queue Input Register
ADC_QINR0_ENSI	SET	0
ADC_QINR0_EXTR	SET	0
ADC_QINR0_REQCHNR	SET	0
ADC_QINR0_RF	SET	0

; RMAP=0 PAGE=6 - ADC Source 0 Queue Mode Register
ADC_QMR0_CEV	SET	0
ADC_QMR0_CLRV	SET	0
ADC_QMR0_ENGT	SET	0
ADC_QMR0_ENTR	SET	0
ADC_QMR0_FLUSH	SET	0
ADC_QMR0_TREV	SET	0
ADC_QMR0_TRMD	SET	0

; RMAP=0 PAGE=6 - ADC Source 0 Queue Status Register
ADC_QSR0_EMPTY	SET	0
ADC_QSR0_EV	SET	0

; RMAP=0 PAGE=4 - ADC Result 0 Control Register
ADC_RCR0_DRCTR	SET	0
ADC_RCR0_FEN	SET	0
ADC_RCR0_IEN	SET	0
ADC_RCR0_VFCTR	SET	0
ADC_RCR0_WFR	SET	0

; RMAP=0 PAGE=4 - ADC Result 1 Control Register
ADC_RCR1_DRCTR	SET	0
ADC_RCR1_FEN	SET	0
ADC_RCR1_IEN	SET	0
ADC_RCR1_VFCTR	SET	0
ADC_RCR1_WFR	SET	0

; RMAP=0 PAGE=4 - ADC Result 2 Control Register
ADC_RCR2_DRCTR	SET	0
ADC_RCR2_FEN	SET	0
ADC_RCR2_IEN	SET	0
ADC_RCR2_VFCTR	SET	0
ADC_RCR2_WFR	SET	0

; RMAP=0 PAGE=4 - ADC Result 3 Control Register
ADC_RCR3_DRCTR	SET	0
ADC_RCR3_FEN	SET	0
ADC_RCR3_IEN	SET	0
ADC_RCR3_VFCTR	SET	0
ADC_RCR3_WFR	SET	0

; RMAP=0 PAGE=2 - ADC Result 0 Register High
ADC_RESR0H_RESULT[9:2]	SET	0

; RMAP=0 PAGE=2 - ADC Result 0 Register Low
ADC_RESR0L_CHNR	SET	0
ADC_RESR0L_DRC	SET	0
ADC_RESR0L_RESULT[1:0]	SET	0
ADC_RESR0L_VF	SET	0

; RMAP=0 PAGE=2 - ADC Result 1 Register High
ADC_RESR1H_RESULT[9:2]	SET	0

; RMAP=0 PAGE=2 - ADC Result 1 Register Low
ADC_RESR1L_CHNR	SET	0
ADC_RESR1L_DRC	SET	0
ADC_RESR1L_RESULT[1:0]	SET	0
ADC_RESR1L_VF	SET	0

; RMAP=0 PAGE=2 - ADC Result 2 Register High
ADC_RESR2H_RESULT[9:2]	SET	0

; RMAP=0 PAGE=2 - ADC Result 2 Register Low
ADC_RESR2L_CHNR	SET	0
ADC_RESR2L_DRC	SET	0
ADC_RESR2L_RESULT[1:0]	SET	0
ADC_RESR2L_VF	SET	0

; RMAP=0 PAGE=2 - ADC Result 3 Register High
ADC_RESR3H_RESULT[9:2]	SET	0

; RMAP=0 PAGE=2 - ADC Result 3 Register Low
ADC_RESR3L_CHNR	SET	0
ADC_RESR3L_DRC	SET	0
ADC_RESR3L_RESULT[1:0]	SET	0
ADC_RESR3L_VF	SET	0

; RMAP=0 PAGE=3 - ADC Result 0 View A Register High
ADC_RESRA0H_RESULT[10:3]	SET	0

; RMAP=0 PAGE=3 - ADC Result 0 View A Register Low
ADC_RESRA0L_CHNR	SET	0
ADC_RESRA0L_DRC	SET	0
ADC_RESRA0L_RESULT[2:0]	SET	0
ADC_RESRA0L_VF	SET	0

; RMAP=0 PAGE=3 - ADC Result 1 View A Register High
ADC_RESRA1H_RESULT[10:3]	SET	0

; RMAP=0 PAGE=3 - ADC Result 1 View A Register Low
ADC_RESRA1L_CHNR	SET	0
ADC_RESRA1L_DRC	SET	0
ADC_RESRA1L_RESULT[2:0]	SET	0
ADC_RESRA1L_VF	SET	0

; RMAP=0 PAGE=3 - ADC Result 2 View A Register High
ADC_RESRA2H_RESULT[10:3]	SET	0

; RMAP=0 PAGE=3 - ADC Result 2 View A Register Low
ADC_RESRA2L_CHNR	SET	0
ADC_RESRA2L_DRC	SET	0
ADC_RESRA2L_RESULT[2:0]	SET	0
ADC_RESRA2L_VF	SET	0

; RMAP=0 PAGE=3 - ADC Result 3 View A Register High
ADC_RESRA3H_RESULT[10:3]	SET	0

; RMAP=0 PAGE=3 - ADC Result 3 View A Register Low
ADC_RESRA3L_CHNR	SET	0
ADC_RESRA3L_DRC	SET	0
ADC_RESRA3L_RESULT[2:0]	SET	0
ADC_RESRA3L_VF	SET	0

; RMAP=0 PAGE=4 - ADC Valid Flag Clear Register
ADC_VFCR_VFC0	SET	0
ADC_VFCR_VFC1	SET	0
ADC_VFCR_VFC2	SET	0
ADC_VFCR_VFC3	SET	0

; RMAP=x  - CPU Accumulator Register
A_ACC0	SET	0
A_ACC1	SET	0
A_ACC2	SET	0
A_ACC3	SET	0
A_ACC4	SET	0
A_ACC5	SET	0
A_ACC6	SET	0
A_ACC7	SET	0

; RMAP=0 PAGE=0 - SCU Baud Rate Control Register
BCON_BGSEL	SET	0
BCON_BREN	SET	0
BCON_BRPRE	SET	0
BCON_R	SET	0
BCON_T2EXIS	SET	0

; RMAP=0 PAGE=0 - SCU Baud Rate Timer/Reload Register
BG_BR_VALUE	SET	0

; RMAP=x  - CPU B Register
B_B0	SET	0
B_B1	SET	0
B_B2	SET	0
B_B3	SET	0
B_B4	SET	0
B_B5	SET	0
B_B6	SET	0
B_B7	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC60 High
CCU6_CC60RH_CC60VH	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC60 Low
CCU6_CC60RL_CC60VL	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC60 High
CCU6_CC60SRH_CC60SH	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC60 Low
CCU6_CC60SRL_CC60SL	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC61 High
CCU6_CC61RH_CC61VH	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC61 Low
CCU6_CC61RL_CC61VL	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC61 High
CCU6_CC61SRH_CC61SH	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC61 Low
CCU6_CC61SRL_CC61SL	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC62 High
CCU6_CC62RH_CC62VH	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC62 Low
CCU6_CC62RL_CC62VL	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC62 High
CCU6_CC62SRH_CC62SH	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC62 Low
CCU6_CC62SRL_CC62SL	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC63 High
CCU6_CC63RH_CC63VH	SET	0

; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC63 Low
CCU6_CC63RL_CC63VL	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC63 High
CCU6_CC63SRH_CC63SH	SET	25

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC63 Low
CCU6_CC63SRL_CC63SL	SET	154

; RMAP=0 PAGE=0 - CCU6 Compare State Modification Register High
CCU6_CMPMODIFH_MCC60R	SET	0
CCU6_CMPMODIFH_MCC61R	SET	0
CCU6_CMPMODIFH_MCC62R	SET	0
CCU6_CMPMODIFH_MCC63R	SET	0

; RMAP=0 PAGE=0 - CCU6 Compare State Modification Register Low
CCU6_CMPMODIFL_MCC60S	SET	0
CCU6_CMPMODIFL_MCC61S	SET	0
CCU6_CMPMODIFL_MCC62S	SET	0
CCU6_CMPMODIFL_MCC63S	SET	0

; RMAP=0 PAGE=3 - CCU6 Compare State Register High
CCU6_CMPSTATH_CC60PS	SET	0
CCU6_CMPSTATH_CC61PS	SET	0
CCU6_CMPSTATH_CC62PS	SET	0
CCU6_CMPSTATH_COUT60PS	SET	0
CCU6_CMPSTATH_COUT61PS	SET	0
CCU6_CMPSTATH_COUT62PS	SET	0
CCU6_CMPSTATH_COUT63PS	SET	0
CCU6_CMPSTATH_T13IM	SET	0

; RMAP=0 PAGE=3 - CCU6 Compare State Register Low
CCU6_CMPSTATL_CC60ST	SET	0
CCU6_CMPSTATL_CC61ST	SET	0
CCU6_CMPSTATL_CC62ST	SET	0
CCU6_CMPSTATL_CC63ST	SET	0
CCU6_CMPSTATL_CCPOS0	SET	0
CCU6_CMPSTATL_CCPOS1	SET	0
CCU6_CMPSTATL_CCPOS2	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Enable Register High
CCU6_IENH_ENCHE	SET	0
CCU6_IENH_ENIDLE	SET	0
CCU6_IENH_ENSTR	SET	0
CCU6_IENH_ENT13CM	SET	0
CCU6_IENH_ENT13PM	SET	1
CCU6_IENH_ENTRPF	SET	0
CCU6_IENH_ENWHE	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Enable Register Low
CCU6_IENL_ENCC60F	SET	0
CCU6_IENL_ENCC60R	SET	0
CCU6_IENL_ENCC61F	SET	0
CCU6_IENL_ENCC61R	SET	0
CCU6_IENL_ENCC62F	SET	0
CCU6_IENL_ENCC62R	SET	0
CCU6_IENL_ENT12OM	SET	0
CCU6_IENL_ENT12PM	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Node Pointer Register High
CCU6_INPH_INPERR	SET	0
CCU6_INPH_INPT12	SET	0
CCU6_INPH_INPT13	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Node Pointer Register Low
CCU6_INPL_INPCC60	SET	0
CCU6_INPL_INPCC61	SET	0
CCU6_INPL_INPCC62	SET	0
CCU6_INPL_INPCHE	SET	0

; RMAP=0 PAGE=3 - CCU6 Capture/Compare Interrupt Status Register High
CCU6_ISH_CHE	SET	0
CCU6_ISH_IDLE	SET	0
CCU6_ISH_STR	SET	0
CCU6_ISH_T13CM	SET	0
CCU6_ISH_T13PM	SET	0
CCU6_ISH_TRPF	SET	0
CCU6_ISH_TRPS	SET	0
CCU6_ISH_WHE	SET	0

; RMAP=0 PAGE=3 - CCU6 Capture/Compare Interrupt Status Register Low
CCU6_ISL_ICC60F	SET	0
CCU6_ISL_ICC60R	SET	0
CCU6_ISL_ICC61F	SET	0
CCU6_ISL_ICC61R	SET	0
CCU6_ISL_ICC62F	SET	0
CCU6_ISL_ICC62R	SET	0
CCU6_ISL_T12OM	SET	0
CCU6_ISL_T12PM	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Interrupt Status Reset Register High
CCU6_ISRH_RCHE	SET	0
CCU6_ISRH_RIDLE	SET	0
CCU6_ISRH_RSTR	SET	0
CCU6_ISRH_RT13CM	SET	0
CCU6_ISRH_RT13PM	SET	0
CCU6_ISRH_RTRPF	SET	0
CCU6_ISRH_RWHE	SET	0

; RMAP=0 PAGE=0 - CCU6 Capture/Compare Interrupt Status Reset Register Low
CCU6_ISRL_RCC60F	SET	0
CCU6_ISRL_RCC60R	SET	0
CCU6_ISRL_RCC61F	SET	0
CCU6_ISRL_RCC61R	SET	0
CCU6_ISRL_RCC62F	SET	0
CCU6_ISRL_RCC62R	SET	0
CCU6_ISRL_RT12OM	SET	0
CCU6_ISRL_RT12PM	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Status Set Register High
CCU6_ISSH_SCHE	SET	0
CCU6_ISSH_SIDLE	SET	0
CCU6_ISSH_SSTR	SET	0
CCU6_ISSH_ST13CM	SET	0
CCU6_ISSH_ST13PM	SET	0
CCU6_ISSH_STRPF	SET	0
CCU6_ISSH_SWHC	SET	0
CCU6_ISSH_SWHE	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Status Set Register Low
CCU6_ISSL_SCC60F	SET	0
CCU6_ISSL_SCC60R	SET	0
CCU6_ISSL_SCC61F	SET	0
CCU6_ISSL_SCC61R	SET	0
CCU6_ISSL_SCC62F	SET	0
CCU6_ISSL_SCC62R	SET	0
CCU6_ISSL_ST12OM	SET	0
CCU6_ISSL_ST12PM	SET	0

; RMAP=0 PAGE=2 - CCU6 Multi-Channel Mode Control Register
CCU6_MCMCTR_SWSEL	SET	0
CCU6_MCMCTR_SWSYN	SET	0

; RMAP=0 PAGE=3 - CCU6 Multi-Channel Mode Output Register High
CCU6_MCMOUTH_CURH	SET	0
CCU6_MCMOUTH_EXPH	SET	0

; RMAP=0 PAGE=3 - CCU6 Multi-Channel Mode Output Register Low
CCU6_MCMOUTL_MCMP	SET	0
CCU6_MCMOUTL_R	SET	0

; RMAP=0 PAGE=0 - CCU6 Multi-Channel Mode Output Shadow Register High
CCU6_MCMOUTSH_CURHS	SET	0
CCU6_MCMOUTSH_EXPHS	SET	0
CCU6_MCMOUTSH_STRHP	SET	0

; RMAP=0 PAGE=0 - CCU6 Multi-Channel Mode Output Shadow Register Low
CCU6_MCMOUTSL_MCMPS	SET	0
CCU6_MCMOUTSL_STRMCM	SET	0

; RMAP=0 PAGE=2 - CCU6 Modulation Control Register High
CCU6_MODCTRH_ECT13O	SET	1
CCU6_MODCTRH_T13MODEN	SET	0

; RMAP=0 PAGE=2 - CCU6 Modulation Control Register Low
CCU6_MODCTRL_MCMEN	SET	0
CCU6_MODCTRL_T12MODEN	SET	0

; RMAP=0  - CCU6 Page Register
CCU6_PAGE_OP	SET	0
CCU6_PAGE_PAGE	SET	0
CCU6_PAGE_STNR	SET	0

; RMAP=0 PAGE=3 - CCU6 Port Input Select 0 Register High
CCU6_PISEL0H_ISPOS0	SET	0
CCU6_PISEL0H_ISPOS1	SET	0
CCU6_PISEL0H_ISPOS2	SET	0
CCU6_PISEL0H_IST12HR	SET	0

; RMAP=0 PAGE=3 - CCU6 Port Input Select 0 Register Low
CCU6_PISEL0L_ISCC60	SET	0
CCU6_PISEL0L_ISCC61	SET	0
CCU6_PISEL0L_ISCC62	SET	0
CCU6_PISEL0L_ISTRP	SET	0

; RMAP=0 PAGE=3 - CCU6 Port Input Select 2 Register
CCU6_PISEL2_IST13HR	SET	0

; RMAP=0 PAGE=2 - CCU6 Passive State Level Register
CCU6_PSLR_PSL	SET	0
CCU6_PSLR_PSL63	SET	0

; RMAP=0 PAGE=1 - CCU6 Dead-Time Control Register for Timer T12 High
CCU6_T12DTCH_DTE0	SET	0
CCU6_T12DTCH_DTE1	SET	0
CCU6_T12DTCH_DTE2	SET	0
CCU6_T12DTCH_DTR0	SET	0
CCU6_T12DTCH_DTR1	SET	0
CCU6_T12DTCH_DTR2	SET	0

; RMAP=0 PAGE=1 - CCU6 Dead-Time Control Register for Timer T12 Low
CCU6_T12DTCL_DTM	SET	1

; RMAP=0 PAGE=3 - CCU6 Timer T12 Counter Register High
CCU6_T12H_T12CVH	SET	0

; RMAP=0 PAGE=3 - CCU6 Timer T12 Counter Register Low
CCU6_T12L_T12CVL	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Mode Select Register High
CCU6_T12MSELH_DBYP	SET	0
CCU6_T12MSELH_HSYNC	SET	0
CCU6_T12MSELH_MSEL62	SET	0

; RMAP=0 PAGE=2 - CCU6 Capture/Compare Mode Select Register Low
CCU6_T12MSELL_MSEL60	SET	0
CCU6_T12MSELL_MSEL61	SET	0

; RMAP=0 PAGE=1 - CCU6 Timer T12 Period Register High
CCU6_T12PRH_T12PVH	SET	0

; RMAP=0 PAGE=1 - CCU6 Timer T12 Period Register Low
CCU6_T12PRL_T12PVL	SET	1

; RMAP=0 PAGE=3 - CCU6 Timer T13 Counter Register High
CCU6_T13H_T13CVH	SET	0

; RMAP=0 PAGE=3 - CCU6 Timer T13 Counter Register Low
CCU6_T13L_T13CVL	SET	0

; RMAP=0 PAGE=1 - CCU6 Timer T13 Period Register High
CCU6_T13PRH_T13PVH	SET	255

; RMAP=0 PAGE=1 - CCU6 Timer T13 Period Register Low
CCU6_T13PRL_T13PVL	SET	255

; RMAP=0 PAGE=1 - CCU6 Timer Control 0 Register High
CCU6_TCTR0H_STE13	SET	0
CCU6_TCTR0H_T13CLK	SET	7
CCU6_TCTR0H_T13PRE	SET	0
CCU6_TCTR0H_T13R	SET	0

; RMAP=0 PAGE=1 - CCU6 Timer Control 0 Register Low
CCU6_TCTR0L_CDIR	SET	0
CCU6_TCTR0L_CTM	SET	0
CCU6_TCTR0L_STE12	SET	0
CCU6_TCTR0L_T12CLK	SET	0
CCU6_TCTR0L_T12PRE	SET	0
CCU6_TCTR0L_T12R	SET	0

; RMAP=0 PAGE=2 - CCU6 Timer Control 2 Register High
CCU6_TCTR2H_T12RSEL	SET	0
CCU6_TCTR2H_T13RSEL	SET	0

; RMAP=0 PAGE=2 - CCU6 Timer Control 2 Register Low
CCU6_TCTR2L_T12SSC	SET	0
CCU6_TCTR2L_T13SSC	SET	0
CCU6_TCTR2L_T13TEC	SET	0
CCU6_TCTR2L_T13TED	SET	1

; RMAP=0 PAGE=0 - CCU6 Timer Control 4 Register High
CCU6_TCTR4H_T13RES	SET	0
CCU6_TCTR4H_T13RR	SET	0
CCU6_TCTR4H_T13RS	SET	0
CCU6_TCTR4H_T13STD	SET	0
CCU6_TCTR4H_T13STR	SET	0

; RMAP=0 PAGE=0 - CCU6 Timer Control 4 Register Low
CCU6_TCTR4L_DTRES	SET	0
CCU6_TCTR4L_T12RES	SET	0
CCU6_TCTR4L_T12RR	SET	0
CCU6_TCTR4L_T12RS	SET	0
CCU6_TCTR4L_T12STD	SET	0
CCU6_TCTR4L_T12STR	SET	0

; RMAP=0 PAGE=2 - CCU6 Trap Control Register High
CCU6_TRPCTRH_TRPEN	SET	0
CCU6_TRPCTRH_TRPEN13	SET	0
CCU6_TRPCTRH_TRPPEN	SET	0

; RMAP=0 PAGE=2 - CCU6 Trap Control Register Low
CCU6_TRPCTRL_TRPM0	SET	0
CCU6_TRPCTRL_TRPM1	SET	0
CCU6_TRPCTRL_TRPM2	SET	0

; RMAP=0 PAGE=1 - SCU Clock Control Register
CMCON_CLKREL	SET	0

; RMAP=x  - CPU Data Pointer Register High
DPH_DPH0	SET	0
DPH_DPH1	SET	0
DPH_DPH2	SET	0
DPH_DPH3	SET	0
DPH_DPH4	SET	0
DPH_DPH5	SET	0
DPH_DPH6	SET	0
DPH_DPH7	SET	0

; RMAP=x  - CPU Data Pointer Register Low
DPL_DPL0	SET	0
DPL_DPL1	SET	0
DPL_DPL2	SET	0
DPL_DPL3	SET	0
DPL_DPL4	SET	0
DPL_DPL5	SET	0
DPL_DPL6	SET	0
DPL_DPL7	SET	0

; RMAP=x  - CPU Extended Operation Register
EO_DPSEL0	SET	0
EO_TRAP_EN	SET	0

; RMAP=0 PAGE=0 - SCU External Interrupt Control Register 0
EXICON0_EXINT0	SET	0
EXICON0_EXINT1	SET	0
EXICON0_EXINT2	SET	0
EXICON0_EXINT3	SET	0

; RMAP=0 PAGE=0 - SCU External Interrupt Control Register 1
EXICON1_EXINT4	SET	0
EXICON1_EXINT5	SET	0
EXICON1_EXINT6	SET	0

; RMAP=0 PAGE=1 - SCU Flash Error Address Register High
FEAH_ECCERRADDR[15:8]	SET	0

; RMAP=0 PAGE=1 - SCU Flash Error Address Register Low
FEAL_ECCERRADDR[7:0]	SET	0

; RMAP=1  - OCDS Hardware Breakpoints Data Register
HWBPDR_HWBPXX	SET	0

; RMAP=1  - OCDS Hardware Breakpoints Select Register
HWBPSR_BPSEL	SET	0
HWBPSR_BPSEL_P	SET	0

; RMAP=0 PAGE=1 - SCU Identity Register
ID_PRODID	SET	0
ID_VERID	SET	0

; RMAP=x  - CPU Interrupt Enable 0 Register
IEN0_EA	SET	1
IEN0_ES	SET	0
IEN0_ET0	SET	1
IEN0_ET1	SET	1
IEN0_ET2	SET	1
IEN0_EX0	SET	0
IEN0_EX1	SET	0

; RMAP=x  - CPU Module Interrupt Enable 1 Register
IEN1_EADC	SET	0
IEN1_ECCIP0	SET	1
IEN1_ECCIP1	SET	0
IEN1_ECCIP2	SET	0
IEN1_ECCIP3	SET	0
IEN1_ESSC	SET	0
IEN1_EX2	SET	0
IEN1_EXM	SET	0

; RMAP=x  - CPU Interrupt Priority 1 Register
IP1_PADC	SET	0
IP1_PCCIP0	SET	1
IP1_PCCIP1	SET	0
IP1_PCCIP2	SET	0
IP1_PCCIP3	SET	0
IP1_PSSC	SET	0
IP1_PX2	SET	0
IP1_PXM	SET	0

; RMAP=x  - CPU Interrupt Priority 1 High Register
IPH1_PADCH	SET	0
IPH1_PCCIP0H	SET	0
IPH1_PCCIP1H	SET	0
IPH1_PCCIP2H	SET	0
IPH1_PCCIP3H	SET	0
IPH1_PSSCH	SET	0
IPH1_PX2H	SET	0
IPH1_PXMH	SET	0

; RMAP=x  - CPU Interrupt Priority High Register
IPH_PSH	SET	0
IPH_PT0H	SET	0
IPH_PT1H	SET	0
IPH_PT2H	SET	0
IPH_PX0H	SET	0
IPH_PX1H	SET	0

; RMAP=x  - CPU Interrupt Priority Register
IP_PS	SET	0
IP_PT0	SET	0
IP_PT1	SET	0
IP_PT2	SET	0
IP_PX0	SET	0
IP_PX1	SET	0

; RMAP=0 PAGE=0 - SCU Interrupt Request Register 0
IRCON0_EXINT0	SET	0
IRCON0_EXINT1	SET	0
IRCON0_EXINT2	SET	0
IRCON0_EXINT3	SET	0
IRCON0_EXINT4	SET	0
IRCON0_EXINT5	SET	0
IRCON0_EXINT6	SET	0

; RMAP=0 PAGE=0 - SCU Interrupt Request Register 1
IRCON1_ADCSRC0	SET	0
IRCON1_ADCSRC1	SET	0
IRCON1_EIR	SET	0
IRCON1_RIR	SET	0
IRCON1_TIR	SET	0

; RMAP=1  - OCDS BreakPoints Control Register
MMBPCR_HWB0C	SET	0
MMBPCR_HWB1C	SET	0
MMBPCR_HWB2C	SET	0
MMBPCR_HWB3C	SET	0
MMBPCR_SWBC	SET	0

; RMAP=1  - OCDS Monitor Mode Control 2 Register
MMCR2_EXBC	SET	0
MMCR2_EXBC_P	SET	0
MMCR2_JENA	SET	0
MMCR2_MBCON	SET	0
MMCR2_MBCON_P	SET	0
MMCR2_MMEP	SET	0
MMCR2_MMEP_P	SET	0
MMCR2_MMODE	SET	0

; RMAP=1  - OCDS Monitor Mode Control Register
MMCR_MEXIT	SET	0
MMCR_MEXIT_P	SET	0
MMCR_MRAMS	SET	0
MMCR_MRAMS_P	SET	0
MMCR_MSTEP	SET	0
MMCR_MSTEP_P	SET	0
MMCR_RRF	SET	0
MMCR_TRF	SET	0

; RMAP=1  - OCDS Monitor Mode Data Transfer Register Receive
MMDR_MMRR	SET	0

; RMAP=1  - OCDS Monitor Mode Interrupt Control Register
MMICR_DRETR	SET	0
MMICR_DVECT	SET	0
MMICR_MMUIE	SET	0
MMICR_MMUIE_P	SET	0
MMICR_RRIE	SET	0
MMICR_RRIE_P	SET	0

; RMAP=1  - OCDS Monitor Mode Status Register
MMSR_EXBF	SET	0
MMSR_HWB0F	SET	0
MMSR_HWB1F	SET	0
MMSR_HWB2F	SET	0
MMSR_HWB3F	SET	0
MMSR_MBCAM	SET	0
MMSR_MBCIN	SET	0
MMSR_SWBF	SET	0

; RMAP=0 PAGE=0 - SCU Peripheral Input Select Register
MODPISEL_EXINT0IS	SET	0
MODPISEL_JTAGTCKS	SET	0
MODPISEL_JTAGTDIS	SET	0
MODPISEL_URRIS	SET	0

; RMAP=0 PAGE=0 - SCU NMI Control Register
NMICON_NMIECC	SET	0
NMICON_NMIFLASHTIMER	SET	0
NMICON_NMIOCDS	SET	0
NMICON_NMIPLL	SET	0
NMICON_NMIVDD	SET	0
NMICON_NMIVDDP	SET	0
NMICON_NMIWDT	SET	0

; RMAP=0 PAGE=0 - SCU NMI Status Register
NMISR_FNMIECC	SET	0
NMISR_FNMIFLASHTIMER	SET	0
NMISR_FNMIOCDS	SET	0
NMISR_FNMIPLL	SET	0
NMISR_FNMIVDD	SET	0
NMISR_FNMIVDDP	SET	0
NMISR_FNMIWDT	SET	0

; RMAP=0 PAGE=1 - SCU OSC Control Register
OSC_CON_ORDRES	SET	0
OSC_CON_OSCPD	SET	0
OSC_CON_OSCR	SET	0
OSC_CON_OSCSS	SET	0
OSC_CON_XPD	SET	1

; RMAP=0 PAGE=2 - PORT P0 Alternate Select 0 Register
P0_ALTSEL0_P0	SET	0
P0_ALTSEL0_P1	SET	0
P0_ALTSEL0_P2	SET	0
P0_ALTSEL0_P3	SET	0
P0_ALTSEL0_P4	SET	0
P0_ALTSEL0_P5	SET	0

; RMAP=0 PAGE=2 - PORT P0 Alternate Select 1 Register
P0_ALTSEL1_P0	SET	0
P0_ALTSEL1_P1	SET	0
P0_ALTSEL1_P2	SET	0
P0_ALTSEL1_P3	SET	0
P0_ALTSEL1_P4	SET	0
P0_ALTSEL1_P5	SET	0

; RMAP=0 PAGE=0 - PORT P0 Data Register
P0_DATA_P0	SET	0
P0_DATA_P1	SET	0
P0_DATA_P2	SET	0
P0_DATA_P3	SET	0
P0_DATA_P4	SET	0
P0_DATA_P5	SET	0

; RMAP=0 PAGE=0 - PORT P0 Direction Register
P0_DIR_P0	SET	0
P0_DIR_P1	SET	0
P0_DIR_P2	SET	0
P0_DIR_P3	SET	0
P0_DIR_P4	SET	0
P0_DIR_P5	SET	0

; RMAP=0 PAGE=3 - PORT P0 Open Drain Control Register
P0_OD_P0	SET	0
P0_OD_P1	SET	0
P0_OD_P2	SET	0
P0_OD_P3	SET	0
P0_OD_P4	SET	0
P0_OD_P5	SET	0

; RMAP=0 PAGE=1 - PORT P0 Pull-Up/Pull-Down Enable Register
P0_PUDEN_P0	SET	0
P0_PUDEN_P1	SET	0
P0_PUDEN_P2	SET	1
P0_PUDEN_P3	SET	0
P0_PUDEN_P4	SET	0
P0_PUDEN_P5	SET	0

; RMAP=0 PAGE=1 - PORT P0 Pull-Up/Pull-Down Select Register
P0_PUDSEL_P0	SET	1
P0_PUDSEL_P1	SET	1
P0_PUDSEL_P2	SET	1
P0_PUDSEL_P3	SET	1
P0_PUDSEL_P4	SET	1
P0_PUDSEL_P5	SET	1

; RMAP=0 PAGE=2 - PORT P1 Alternate Select 0 Register
P1_ALTSEL0_P0	SET	0
P1_ALTSEL0_P1	SET	0
P1_ALTSEL0_P5	SET	0
P1_ALTSEL0_P6	SET	0
P1_ALTSEL0_P7	SET	0

; RMAP=0 PAGE=2 - PORT P1 Alternate Select 1 Register
P1_ALTSEL1_P0	SET	0
P1_ALTSEL1_P1	SET	0
P1_ALTSEL1_P5	SET	0
P1_ALTSEL1_P6	SET	0
P1_ALTSEL1_P7	SET	0

; RMAP=0 PAGE=0 - PORT P1 Data Register
P1_DATA_P0	SET	0
P1_DATA_P1	SET	0
P1_DATA_P5	SET	0
P1_DATA_P6	SET	0
P1_DATA_P7	SET	0

; RMAP=0 PAGE=0 - PORT P1 Direction Register
P1_DIR_P0	SET	0
P1_DIR_P1	SET	0
P1_DIR_P5	SET	0
P1_DIR_P6	SET	0
P1_DIR_P7	SET	0

; RMAP=0 PAGE=3 - PORT P1 Open Drain Control Register
P1_OD_P0	SET	0
P1_OD_P1	SET	0
P1_OD_P5	SET	0
P1_OD_P6	SET	0
P1_OD_P7	SET	0

; RMAP=0 PAGE=1 - PORT P1 Pull-Up/Pull-Down Enable Register
P1_PUDEN_P0	SET	1
P1_PUDEN_P1	SET	1
P1_PUDEN_P5	SET	1
P1_PUDEN_P6	SET	1
P1_PUDEN_P7	SET	1

; RMAP=0 PAGE=1 - PORT P1 Pull-Up/Pull-Down Select Register
P1_PUDSEL_P0	SET	1
P1_PUDSEL_P1	SET	1
P1_PUDSEL_P5	SET	1
P1_PUDSEL_P6	SET	1
P1_PUDSEL_P7	SET	1

; RMAP=0 PAGE=0 - PORT P2 Data Register
P2_DATA_P0	SET	0
P2_DATA_P1	SET	0
P2_DATA_P2	SET	0
P2_DATA_P3	SET	0
P2_DATA_P4	SET	0
P2_DATA_P5	SET	0
P2_DATA_P6	SET	0
P2_DATA_P7	SET	0

; RMAP=0 PAGE=1 - PORT P2 Pull-Up/Pull-Down Enable Register
P2_PUDEN_P0	SET	0
P2_PUDEN_P1	SET	0
P2_PUDEN_P2	SET	0
P2_PUDEN_P3	SET	0
P2_PUDEN_P4	SET	0
P2_PUDEN_P5	SET	0
P2_PUDEN_P6	SET	0
P2_PUDEN_P7	SET	0

; RMAP=0 PAGE=1 - PORT P2 Pull-Up/Pull-Down Select Register
P2_PUDSEL_P0	SET	1
P2_PUDSEL_P1	SET	1
P2_PUDSEL_P2	SET	1
P2_PUDSEL_P3	SET	1
P2_PUDSEL_P4	SET	1
P2_PUDSEL_P5	SET	1
P2_PUDSEL_P6	SET	1
P2_PUDSEL_P7	SET	1

; RMAP=0 PAGE=2 - PORT P3 Alternate Select 0 Register
P3_ALTSEL0_P0	SET	0
P3_ALTSEL0_P1	SET	0
P3_ALTSEL0_P2	SET	0
P3_ALTSEL0_P3	SET	0
P3_ALTSEL0_P4	SET	0
P3_ALTSEL0_P5	SET	0
P3_ALTSEL0_P6	SET	0
P3_ALTSEL0_P7	SET	1

; RMAP=0 PAGE=2 - PORT P3 Alternate Select 1 Register
P3_ALTSEL1_P0	SET	0
P3_ALTSEL1_P1	SET	0
P3_ALTSEL1_P2	SET	0
P3_ALTSEL1_P3	SET	0
P3_ALTSEL1_P4	SET	0
P3_ALTSEL1_P5	SET	0
P3_ALTSEL1_P6	SET	0
P3_ALTSEL1_P7	SET	0

; RMAP=0 PAGE=0 - PORT P3 Data Register
P3_DATA_P0	SET	0
P3_DATA_P1	SET	0
P3_DATA_P2	SET	0
P3_DATA_P3	SET	0
P3_DATA_P4	SET	0
P3_DATA_P5	SET	0
P3_DATA_P6	SET	0
P3_DATA_P7	SET	0

; RMAP=0 PAGE=0 - PORT P3 Direction Register
P3_DIR_P0	SET	1
P3_DIR_P1	SET	1
P3_DIR_P2	SET	1
P3_DIR_P3	SET	1
P3_DIR_P4	SET	1
P3_DIR_P5	SET	1
P3_DIR_P6	SET	1
P3_DIR_P7	SET	1

; RMAP=0 PAGE=3 - PORT P3 Open Drain Control Register
P3_OD_P0	SET	1
P3_OD_P1	SET	1
P3_OD_P2	SET	1
P3_OD_P3	SET	1
P3_OD_P4	SET	1
P3_OD_P5	SET	1
P3_OD_P6	SET	1
P3_OD_P7	SET	0

; RMAP=0 PAGE=1 - PORT P3 Pull-Up/Pull-Down Enable Register
P3_PUDEN_P0	SET	1
P3_PUDEN_P1	SET	1
P3_PUDEN_P2	SET	1
P3_PUDEN_P3	SET	1
P3_PUDEN_P4	SET	1
P3_PUDEN_P5	SET	1
P3_PUDEN_P6	SET	1
P3_PUDEN_P7	SET	1

; RMAP=0 PAGE=1 - PORT P3 Pull-Up/Pull-Down Select Register
P3_PUDSEL_P0	SET	1
P3_PUDSEL_P1	SET	1
P3_PUDSEL_P2	SET	1
P3_PUDSEL_P3	SET	1
P3_PUDSEL_P4	SET	1
P3_PUDSEL_P5	SET	1
P3_PUDSEL_P6	SET	1
P3_PUDSEL_P7	SET	1

; RMAP=0 PAGE=1 - SCU Password Register
PASSWD_MODE	SET	0
PASSWD_PASS	SET	0
PASSWD_PROTECT_S	SET	0

; RMAP=x  - CPU Power Control Register
PCON_GF0	SET	0
PCON_GF1	SET	0
PCON_IDLE	SET	0
PCON_SMOD	SET	0

; RMAP=0 PAGE=1 - SCU PLL Control Register
PLL_CON_LOCK	SET	0
PLL_CON_NDIV	SET	2
PLL_CON_OSCDISC	SET	0
PLL_CON_RESLD	SET	0
PLL_CON_VCOBYP	SET	0

; RMAP=0 PAGE=1 - SCU Power Mode Control Register 0
PMCON0_PD	SET	0
PMCON0_SD	SET	0
PMCON0_WDTRST	SET	0
PMCON0_WKRS	SET	0
PMCON0_WKSEL	SET	0
PMCON0_WS	SET	0

; RMAP=0 PAGE=1 - SCU Power Mode Control Register 1
PMCON1_ADC_DIS	SET	0
PMCON1_CCU_DIS	SET	0
PMCON1_SSC_DIS	SET	0
PMCON1_T2_DIS	SET	0

; RMAP=0  - PORT Page Register
PORT_PAGE_OP	SET	0
PORT_PAGE_PAGE	SET	0
PORT_PAGE_STNR	SET	0

; RMAP=x  - CPU Program Status Word Register
PSW_AC	SET	0
PSW_CY	SET	0
PSW_F0	SET	0
PSW_F1	SET	0
PSW_OV	SET	0
PSW_P	SET	0
PSW_RS0	SET	0
PSW_RS1	SET	0

; RMAP=x  - CPU Serial Data Buffer Register
SBUF_VAL	SET	0

; RMAP=x  - CPU Serial Channel Control Register
SCON_RB8	SET	0
SCON_REN	SET	0
SCON_RI	SET	0
SCON_SM0	SET	0
SCON_SM1	SET	1
SCON_SM2	SET	0
SCON_TB8	SET	0
SCON_TI	SET	0

; RMAP=0  - SCU Page Register
SCU_PAGE_OP	SET	0
SCU_PAGE_PAGE	SET	0
SCU_PAGE_STNR	SET	0

; RMAP=x  - CPU Stack Pointer Register
SP_SP	SET	0

; RMAP=0  - SSC Baudrate Timer Reload Register High
SSC_BRH_BR_VALUE[15:8]	SET	0

; RMAP=0  - SSC Baudrate Timer Reload Register Low
SSC_BRL_BR_VALUE[7:0]	SET	0

; RMAP=0  - SSC Module Control Register High, Operating Mode
SSC_CONH_O_BE	SET	0
SSC_CONH_O_BSY	SET	0
SSC_CONH_O_EN	SET	0
SSC_CONH_O_MS	SET	0
SSC_CONH_O_PE	SET	0
SSC_CONH_O_RE	SET	0
SSC_CONH_O_TE	SET	0

; RMAP=0 - SSC Module Control Register High Programming Mode
SSC_CONH_P_AREN	SET	0
SSC_CONH_P_BEN	SET	0
SSC_CONH_P_EN	SET	0
SSC_CONH_P_MS	SET	0
SSC_CONH_P_PEN	SET	0
SSC_CONH_P_REN	SET	0
SSC_CONH_P_TEN	SET	0

; RMAP=0  - SSC Module Control Register Low, Operating Mode
SSC_CONL_O_BC	SET	0

; RMAP=0  - SSC Module Control Register Low Programming Mode
SSC_CONL_P_BM	SET	1
SSC_CONL_P_HB	SET	0
SSC_CONL_P_LB	SET	0
SSC_CONL_P_PH	SET	0
SSC_CONL_P_PO	SET	0

; RMAP=0  - SSC Port Input Select Register
SSC_PISEL_CIS	SET	0
SSC_PISEL_MIS	SET	0
SSC_PISEL_SIS	SET	0

; RMAP=0  - SSC Receiver Buffer Register Low
SSC_RBL_RB_VALUE	SET	0

; RMAP=0  - SSC Transmitter Buffer Register Low
SSC_TBL_TB_VALUE	SET	0

; RMAP=x  - SCU System Control Register 0
SYSCON0_RMAP	SET	0

; RMAP=0  - T2 Timer 2 Reload/Capture Register High
T2_RC2H_RC2[15:8]	SET	0

; RMAP=0  - T2 Timer 2 Reload/Capture Register Low
T2_RC2L_RC2[7:0]	SET	0

; RMAP=0  - T2 Timer 2 Control Register
T2_T2CON_CP_RL2	SET	0
T2_T2CON_EXEN2	SET	0
T2_T2CON_EXF2	SET	0
T2_T2CON_TF2	SET	0
T2_T2CON_TR2	SET	1

; RMAP=0  - T2 Timer 2 Register High
T2_T2H_THL2[15:8]	SET	0

; RMAP=0  - T2 Timer 2 Register Low
T2_T2L_THL2[7:0]	SET	0

; RMAP=0  - T2 Timer 2 Mode Register
T2_T2MOD_DCEN	SET	0
T2_T2MOD_EDGESEL	SET	0
T2_T2MOD_PREN	SET	1
T2_T2MOD_T2PRE	SET	4

; RMAP=x  - CPU Timer Control Register
TCON_IE0	SET	0
TCON_IE1	SET	0
TCON_IT0	SET	0
TCON_IT1	SET	0
TCON_TF0	SET	0
TCON_TF1	SET	0
TCON_TR0	SET	1
TCON_TR1	SET	1

; RMAP=x  - CPU Timer 0 Register High
TH0_VAL	SET	0

; RMAP=x  - CPU Timer 1 Register High
TH1_VAL	SET	0

; RMAP=x  - CPU Timer 0 Register Low
TL0_VAL	SET	0

; RMAP=x  - CPU Timer 1 Register Low
TL1_VAL	SET	0

; RMAP=x  - CPU Timer Mode Register
TMOD_GATE0	SET	0
TMOD_GATE1	SET	0
TMOD_T0M	SET	0
TMOD_T1M	SET	0

; RMAP=1  - WDT Watchdog Timer Control Register
WDTCON_WDTEN	SET	0
WDTCON_WDTIN	SET	0
WDTCON_WDTPR	SET	0
WDTCON_WDTRS	SET	0
WDTCON_WINBEN	SET	0

; RMAP=1  - WDT Watchdog Timer Register High
WDTH_WDT[15:8]	SET	0

; RMAP=1  - WDT Watchdog Timer Register Low
WDTL_WDT[7:0]	SET	0

; RMAP=1  - WDT Watchdog Timer Reload Register
WDTREL_WDTREL	SET	0

; RMAP=1  - WDT Watchdog Window-Boundary Count Register
WDTWINB_WDTWINB	SET	0

